ES: ARM Architecture Basics

Understanding ARM architecture is not optional for embedded developers — it is the foundation that explains why embedded code behaves the way it does, why certain optimizations matter, and how to make the most of the hardware available.

This post covers the essential architectural concepts behind ARM processors, from RISC principles to the full Cortex family.

RISC Architecture Principles

ARM processors are built on Reduced Instruction Set Computing (RISC), a design philosophy that emerged from research at UC Berkeley and Stanford in the 1980s. The core insight of RISC is that a processor that does fewer, simpler things per instruction can execute those instructions faster and more efficiently than one that attempts to do complex things in a single step.

ARM's RISC implementation follows these principles:

Simple Instructions

ARM executes simpler instructions compared to CISC architectures like x86. Each instruction maps closely to a small number of micro-operations, enabling high clock frequencies with lower transistor counts.

Fixed-Length Instructions

ARM (32-bit mode) uses fixed 32-bit instructions. This predictable format simplifies instruction decoding — the processor always knows exactly where one instruction ends and the next begins. This contrasts with x86, where instructions can range from 1 to 15 bytes.

Load/Store Architecture

In ARM, all computation happens in registers. Data in memory must be explicitly loaded into a register before it can be used, and results must be explicitly stored back to memory.

x86 (CISC): ADD [memory_address], 5    ; Can add directly to memory
ARM (RISC): LDR R0, [address]          ; Load from memory to register
            ADD R0, R0, #5             ; Add in register
            STR R0, [address]          ; Store result back

This separation makes the memory access pattern explicit and enables aggressive pipelining.

Pipeline Design

ARM processors execute instructions in a pipeline — multiple instructions are in different stages of execution simultaneously.

ARM 3-Stage Pipeline (Cortex-M0):
Stage:    Fetch    Decode    Execute
Cycle 1:  Instr1
Cycle 2:  Instr2   Instr1
Cycle 3:  Instr3   Instr2    Instr1
Cycle 4:  Instr4   Instr3    Instr2

More advanced Cortex-M processors use 5-stage or deeper pipelines for higher throughput. Branches cause pipeline flushes, which is why branch prediction and loop optimization matter in performance-critical code.

Energy Efficiency

The combination of simple instructions, fixed encoding, and load/store architecture results in fewer transistors per operation, which directly translates to lower power consumption — the primary reason ARM dominates battery-powered devices.

Instruction Sets

ARM supports multiple instruction sets, each trading off between performance and code density.

ARM Instruction Set (32-bit)

• The original instruction set.
• All instructions are exactly 32 bits wide.
• Provides the highest performance for compute-intensive workloads.
• Used primarily in Cortex-A application processors.

Thumb Instruction Set (16-bit)

Introduced to reduce memory usage in cost-sensitive devices:

• Instructions are 16 bits wide — 50% smaller than ARM mode instructions.
• The processor executes them with the same registers as ARM mode.
• Code density is roughly 30% better than ARM mode.
• Used heavily in early Cortex-M designs and memory-constrained systems.

Thumb-2 Instruction Set (16/32-bit mixed)

Thumb-2 is the dominant instruction set for Cortex-M processors. It is a superset of Thumb that adds:

• 32-bit Thumb-2 instructions for operations that need full 32-bit encoding
• Retains 16-bit instructions for common operations
• No mode switching required — both widths coexist in the same instruction stream

Code Density vs Performance Trade-off:

ARM:      High performance, larger code size
Thumb:    Smaller code, some performance loss
Thumb-2:  Near-ARM performance with near-Thumb code density

Cortex-M processors exclusively use Thumb-2 — they cannot execute ARM-mode (A32) instructions at all. This is a deliberate simplification that improves chip area efficiency.

Performance Modes

Big.LITTLE Technology

Found in Cortex-A mobile and embedded processors, Big.LITTLE combines two types of cores on the same chip:

+------------------------+     +------------------------+
|    "big" cores         |     |   "LITTLE" cores        |
|    (e.g., Cortex-A77)  |     |   (e.g., Cortex-A55)    |
|    High performance    |     |   Low power             |
|    High power draw     |     |   Energy efficient      |
+------------------------+     +------------------------+
                  ^                   ^
                  |     Scheduler     |
                  +-------------------+

The operating system scheduler dynamically assigns tasks to core types:

• Demanding tasks (video rendering, ML inference) → big cores
• Background tasks (email sync, idle monitoring) → LITTLE cores
• Sleeping between events → LITTLE cores or power-off

This dynamic switching extends battery life dramatically while maintaining burst performance.

Cortex-M Power Efficiency Modes

Cortex-M processors designed for IoT and embedded applications include hardware sleep modes:

These modes are entered via ARM WFI (Wait For Interrupt) and WFE (Wait For Event) instructions:

// Enter sleep mode — core halts until next interrupt
__WFI();

// Enter sleep mode — core halts until event or interrupt
__WFE();

ARM Processor Families

Cortex-M Series

Target applications: Microcontrollers, IoT devices, low-power embedded systems

Cortex-M0   -- Minimal silicon, 32-bit RISC in a tiny MCU (simple sensing)
Cortex-M0+  -- Improved power efficiency, optional MPU (IoT nodes)
Cortex-M3   -- Full Thumb-2, hardware divide, bit-banding (general MCU)
Cortex-M4   -- M3 + DSP extensions + optional FPU (audio, motor control)
Cortex-M7   -- Dual-issue, TCM, high performance MCU (automotive, graphics)
Cortex-M33  -- M4 + TrustZone security (secure IoT)
Cortex-M55  -- M33 + Helium SIMD for ML/DSP (ML on MCU)

Key advantages:

• Thumb-2 instruction set (no ARM mode overhead)
• NVIC with deterministic interrupt latency
• SysTick timer (standard across all Cortex-M)
• Optional FPU, DSP, MPU, TrustZone
• Supports FreeRTOS, Zephyr, and other embedded RTOS

Examples: STM32 (ST), LPC (NXP), SAMD (Microchip), nRF52 (Nordic)

Cortex-A Series

Target applications: High-performance embedded, mobile, consumer electronics

Key features:

• ARMv7-A (32-bit) and ARMv8-A (64-bit AArch64) architectures
• Out-of-order execution for maximum throughput
• Hardware MMU for virtual memory and OS support
• Multi-core support for parallel workloads
• NEON SIMD for multimedia and signal processing

Examples: Qualcomm Snapdragon (phones), Apple A/M-series (iPhone, Mac), Raspberry Pi BCM (single-board computers)

Cortex-R Series

Target applications: Real-time safety-critical systems

Key features:

• Deterministic interrupt latency (hard real-time guarantees)
• Dual-core lockstep — two cores execute the same instructions in parallel; results are compared for error detection (critical for automotive ISO 26262)
• Tightly Coupled Memory (TCM) — dedicated SRAM with zero-wait-state access for deterministic timing
• Error Correcting Code (ECC) memory support

Examples: NXP S32 (automotive), TI TMS570 (safety MCU), Infineon AURIX (powertrain)

ARMv8 and ARMv9 Architectures

ARMv8 — 64-bit Computing

ARMv8 introduced AArch64, the 64-bit execution state:

ARMv8 Execution States:
+------------------+     +------------------+
|    AArch64       |     |    AArch32        |
|    64-bit mode   |     |    32-bit mode    |
|    A64 ISA       |     |    A32/T32 ISA    |
|    31 x 64-bit   |     |    16 x 32-bit    |
|    registers     |     |    registers      |
+------------------+     +------------------+

AArch64 benefits:

ARMv9 — Security and AI

ARMv9 builds on ARMv8 with three major advances:

1. Confidential Compute Architecture (CCA)

Introduces hardware-enforced Realms — isolated execution environments protected even from a compromised hypervisor or OS:

+--------------------+
|   Realm 0 (App A)  |  <-- Isolated by hardware
+--------------------+
|   Realm 1 (App B)  |  <-- Cannot read Realm 0 memory
+--------------------+
|    Normal World    |  <-- Standard OS/apps
+--------------------+

2. Scalable Vector Extension 2 (SVE2)

SVE2 extends vector processing capabilities with variable-length vectors (128 to 2048 bits), enabling more efficient ML inference, signal processing, and data-parallel workloads.

3. Memory Tagging Extension (MTE)

Hardware memory tagging helps detect use-after-free and buffer overflow bugs at runtime with minimal overhead.

Summary: ARM Architecture Key Points

RISC Principles:
- Simple, fixed-length instructions
- Load/store memory model
- Pipeline execution for throughput
- Energy efficient by design

Instruction Sets:
- ARM (32-bit): Full performance
- Thumb (16-bit): Code density
- Thumb-2 (mixed): Best balance — used in all Cortex-M

Processor Families:
- Cortex-M: Microcontrollers, IoT, bare-metal
- Cortex-A: Application processors, Linux, Android
- Cortex-R: Real-time, safety-critical

Architecture Versions:
- ARMv7: Cortex family, Thumb-2, NEON
- ARMv8: AArch64, 64-bit, enhanced SIMD
- ARMv9: CCA security, SVE2, MTE

Final Thoughts

ARM architecture is not a single thing — it is a family of carefully designed processor variants spanning from ultra-low-power IoT microcontrollers to high-performance server chips. The common thread is the RISC philosophy: do simple things efficiently, and do them in a pipeline.

Understanding these fundamentals changes how you write embedded code. You stop treating the processor as a black box and start understanding why certain patterns are fast, why branches are costly, and why sleep modes extend battery life by orders of magnitude.

ARM architecture knowledge turns good embedded code into great embedded code.