ES: From Human Instructions to CPU Reality

After understanding CPU fundamentals — registers, ALU, control unit — the next logical question is:

**How does software actually control this hardware?**

The answer is the Instruction Set Architecture (ISA).

But first let's understand what is the the instruction.

What Is an Instruction?

At the most fundamental level, a CPU understands only binary instructions.

An instruction is a bit pattern that tells the CPU:

• _What_ operation to perform
• _Which_ data to use
• _Where_ the result goes

Example (human view):

LDI R10, 255

Meaning:

Load the value `255` into register `R10`

Instruction as Bits (CPU View)

+------+----------+-----------+
| OPC  | Register | Immediate |
+------+----------+-----------+

**The CPU never sees mnemonics**, It sees only **0s and 1s**.

What Is the Instruction Set Architecture (ISA)?

The ISA is the formal contract between software and the CPU.

It defines:

• All valid instructions
• Registers and their roles
• Data types
• Addressing modes
• Memory model (ordering & visibility rules)
• Instruction binary encoding

Software
   |
   |  ISA Contract
   v
+------------------+
|       CPU        |
| ALU | Reg | CU   |
+------------------+

If software follows the ISA, hardware must execute it correctly.

From C Code to CPU Execution

Let’s connect the full pipeline.

x = y + 1;

Step-by-Step Translation

C Code
  |
  v
Compiler (GCC / Clang)
  |
  v
Assembly (ISA-specific)
  |
  v
Machine Code (binary)
  |
  v
CPU executes bits

Example assembly (simplified):

LDR R1, [y]
ADD R1, R1, #1
STR R1, [x]

Each line maps to one or more ISA-defined instructions.

ISA Classifications (Big Picture)

                    ISA TYPES
                        |
------------------------------------------------
   |      |      |      |      |      |      |
  RISC   CISC   MISC   VLIW   EPIC   OISC   ZISC

RISC (Embedded Dominant)

Reduced Instruction Set Computer (RISC) is an instruction set architecture (ISA) which has fewer cycles per instruction (CPI) than complex instruction set computer (CISC).

• Simple instructions
• Load/store
• Efficient pipelines

Examples:

• AVR (Advanced Virtual RISC):

AVR microcontroller is the most popular category of controller and it is cheap. It is used in many robotic applications.

AVR microcontroller is manufactured by Atmel corporation in the year 1996.

It is based on RISC Instruction set Architecture (ISA) and is also called Advanced Virtual RISC.

AT90S8515 was the initial microcontroller belonging to the AVR family.

• ARM (Advanced RISC):

ARM micro-controller was introduced by Acorn computer organization and is manufactured by Apple, Nvidia, Qualcomm, Motorola, ST Microelectronics, Samsung Electronics, TI etc.

It is the most popular microcontroller and most industries use it for embedded systems as it provides a large set of features and is good to produce devices with excellent appearances.

• RISC-V
• MIPS (Microprocessor without Interlocked Pipelines Stages)

because it pushed hazard handling from hardware into the compiler.

CISC

Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) which has fewer instructions per program than a Reduced instruction set computer (RISC).

• Complex instructions
• Compact code
• Complex decoding

x86-x64 or AMD64 is CISC ISA

MISC

Minimal instruction set computers (MISC) is a processor architecture with a very small number of basic instruction operations and corresponding opcodes.

As a result of this is a smaller instruction set, a smaller and faster instruction set decode unit, and faster operation of individual instructions. The disadvantage is that smaller instruction set always have more sequential dependencies, reducing instruction-level parallelism.

MISC → minimal research

VLIW

Very long instruction word (VLIW) is an instruction set architecture designed to exploit instruction level parallelism (ILP).

Central processing units (CPU, processor) mostly allow programs to specify instructions to execute in sequence only, a VLIW processor allows programs to explicitly specify instructions to execute in parallel.

This design is intended to allow higher performance without the complexity inherent in some other designs.

EPIC

Explicitly parallel instruction computing (EPIC) is an instruction set that permits microprocessors to execute software instructions in parallel by using the compiler, rather than complex on-die circuitry, to control parallel instruction execution.

This was intended to allow simple performance scaling without resorting to higher clock frequencies.

VLIW / EPIC → compiler-driven parallelism

OISC

One instruction set computer (OISC) is an abstract machine that uses only one instruction obviating the need for a machine language opcode.

OISCs have been recommended as guides in teaching computer architecture and have been used as computational models in structural computing research.

ZISC

Zero instruction set computer (ZISC) is a computer architecture based on pattern matching and the absence of (micro-)instructions in the classical sense.

These chips are known for being thought of as comparable to the neural networks being marketed for the number of "synapses" and "neurons"

OISC / ZISC → academic & AI models

Up to this point, we have focused on the CPU and its instruction set—how instructions are encoded, executed, and ordered in memory.

However, a CPU on its own cannot sense the world, store firmware permanently, or interact with external signals.

Instruction (ISA)
      ↓
CPU Core
      ↓
+----------------------+
|   Microcontroller    |
|                      |
|  CPU (ISA)           |
|  Flash / RAM         |
|  Timers              |
|  GPIO                |
|  UART / SPI / I2C    |
|  Clock / Reset       |
+----------------------+

To build a usable embedded system, the CPU must be placed inside a larger system that provides memory, peripherals, and clocking.

This is where the microcontroller enters the picture.